5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS
5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS
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DOI：
10.1109/iceic51217.2021.9369819
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发表时间：
2021-01
期刊：
影响因子：
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通讯作者：
Yudai Ichii;Toshiyuki Inoue;A. Tsuchiya;K. Kishine
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文献类型：
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作者：
Yudai Ichii;Toshiyuki Inoue;A. Tsuchiya;K. Kishine
提出了一种在数据传输系统中采用补偿电路的5 Gb/s四电平脉冲幅度调制（PAM 4）发射机。在PAM 4系统中，信号幅度需要较小的上升和下降时间。为了实现这一点，我们采用了模拟前馈均衡（FFE）的补偿在PAM 4发射机。为了确认所提出的技术的优势，我们制作了一个5 Gb/s的PAM 4发射机IC在180 nm CMOS工艺这项工作。测量的上升和下降时间分别比没有FFE的下降时间小18%和13%。
This paper proposes a 5-Gb/s four-level pulse amplitude modulation (PAM4) transmitter using compensation circuit in data transmission systems. In PAM4 systems, the signal amplitude requires smaller rising and falling times. To achieve this, we adopted an analog feed forward equalizing (FFE) for the compensation in PAM4 transmitter. To confirm the advantage of the proposed technique, we fabricated a 5-Gb/s PAM4 transmitter IC in an 180-nm CMOS process for this work. The measured rising and falling times were 18% and 13% smaller than those without FFE, respectively.