Wrapper design for testing IP cores with multiple clock domains
Wrapper design for testing IP cores with multiple clock domains
复制标题
用于测试具有多个时钟域的 IP 核的包装设计
DOI：
10.1109/date.2004.1268882
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发表时间：
2004
期刊：
影响因子：
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通讯作者：
N. Nicolici
中科院分区：
文献类型：
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作者：
Qiang Xu;N. Nicolici
本文讨论了多时钟域嵌入式内核的可测性问题。所提出的解决方案，基于一种新的核心包装架构，显示了如何多频高速测试响应捕获可以实现使用低速测试仪与高速片上生成的时钟同步。利用实验数据，讨论了测试仪通道数量、测试时间、面积开销和功耗之间的权衡。
This paper addresses the testability problems raised by embedded cores with multiple clock domains. The proposed solution, based on a novel core wrapper architecture, shows how multi-frequency at-speed test response capture can be achieved using low-speed testers synchronized with high-speed on-chip generated clocks. Using experimental data, the trade-offs between the number of tester channels, testing time, area overhead and power dissipation are discussed.