Automated Power Characterization for Run-Time Power Emulation of SoC Designs
Automated Power Characterization for Run-Time Power Emulation of SoC Designs
复制标题
用于 SoC 设计运行时功耗仿真的自动功耗表征
DOI：
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发表时间：
2010
期刊：
影响因子：
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通讯作者：
J. Haid
中科院分区：
文献类型：
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作者：
Christian Bachmann;Andreas Genser;C. Steger;R. Weiss;J. Haid
随着越来越复杂的系统的出现，传统的功率估计方法的使用由于大量的仿真时间而变得不可行。硬件加速功率仿真技术（作为功能仿真的副产品执行功率估计）是解决这个问题的一个很有前途的解决方案。然而，迄今为止，只有很少的注意力被授予的问题，设计一个通用的方法，能够自动启用一个给定的被测系统的功率仿真。在本文中，我们提出了一个自动化的电源特性和建模方法，高层次的电源仿真。我们的方法自动从训练集数据中提取相关的模型参数，并生成相应的功率模型。此外，我们调查的电源模型硬件实现的自动化和自动集成到整个系统的HDL描述。对于一个智能卡控制器测试系统的自动创建的功率模型减少了平均估计误差从11.78%到4.71%相比，手动优化的。
With the advent of increasingly complex systems, the use of traditional power estimation approaches is rendered infeasible due to extensive simulation times. Hardware accelerated power emulation techniques, performing power estimation as a by-product of functional emulation, are a promising solution to this problem. However, only little attention has been awarded so far to the problem of devising a generic methodology capable of automatically enabling the power emulation of a given system-under-test. In this paper, we propose an automated power characterization and modeling methodology for high level power emulation. Our methodology automatically extracts relevant model parameters from training set data and generates an according power model. Furthermore, we investigate the automation of the power model hardware implementation and the automated integration into the overall system’s HDL description. For a smart card controller test-system the automatically created power model reduces the average estimation error from 11.78% to 4.71% as compared to a manually optimized one.