Erasing Core Boundaries for Robust and Configurable Performance
Erasing Core Boundaries for Robust and Configurable Performance
复制标题
消除核心边界以获得稳健且可配置的性能
DOI：
10.1109/micro.2010.30
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发表时间：
2010
期刊：
影响因子：
--
通讯作者：
S. Mahlke
中科院分区：
文献类型：
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作者：
S. Gupta;Shuguang Feng;Amin Ansari;S. Mahlke
单线程性能、可靠性和功率效率是未来多核系统的关键设计挑战。虽然已经提出了点解决方案来解决这些问题，但需要对多核系统的结构进行更根本的更改，以无缝地应对这些挑战。为此，本文提出了核心成因，一个动态自适应的多处理器结构，模糊了个别核心的边界，并鼓励跨核心的性能，容错和定制的处理资源共享。此外，作为这一愿景的体现，本文提供了一个统一的性能可靠性解决方案的细节，可以组装可变宽度的处理器从网络的潜在损坏）流水线阶段级资源。这种设计依赖于互连的灵活性，微架构的创新，和编译器指导的指令转向，合并流水线资源的高单线程性能。同样的灵活性使它能够绕过损坏的组件，实现子核心级的缺陷隔离。总之，所产生的结构由一个流水线阶段级资源池组成，这些资源可以被流畅地分配，以加速单线程性能、吞吐量计算或容忍故障。
Single-thread performance, reliability and power efficiency are critical design challenges of future multicore systems. Although point solutions have been proposed to address these issues, a more fundamental change to the fabric of multicore systems is necessary to seamlessly combat these challenges. Towards this end, this paper proposes Core Genesis, a dynamically adaptive multiprocessor fabric that blurs out individual core boundaries, and encourages resource sharing across cores for performance, fault tolerance and customized processing. Further, as a manifestation of this vision, the paper provides details of a unified performance-reliability solution that can assemble variable-width processors from a network of potentially broken) pipeline stage-level resources. This design relies on interconnection flexibility, micro architectural innovations, and compiler directed instruction steering, to merge pipeline resources for high single-thread performance. The same flexibility enables it to route around broken components, achieving sub-core level defect isolation. Together, the resulting fabric consists of a pool of pipeline stage-level resources that can be fluidly allocated for accelerating single-thread performance, throughput computing, or tolerating failures.