Fabrication of high performance 3C-SiC vertical MOSFETs by reducing planar defects
Fabrication of high performance 3C-SiC vertical MOSFETs by reducing planar defects
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DOI：
10.1002/pssb.200844053
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发表时间：
2008-07-01
影响因子：
1.6
通讯作者：
Hatta, Naoki
中科院分区：
文献类型：
--
作者：
Nagasawa, Hiroyuki;Abe, Masayuki;Hatta, Naoki
在起伏硅衬底上生长3C-SiC可以降低其平面缺陷密度。然而，特定的堆垛层错（SF）仍然存在，其暴露（001）表面上的Si面。这些残余SF增加了用3C-SiC制成的器件中的漏电流。他们可以消除使用先进的SF减少方法称为切换回外延（SBE），结合极性转换同质外延生长。垂直金属氧化物半导体场效应晶体管（MOSFET）是用SBE在3C-SiC上制造的，其尺寸从面积为（30 × 30）μ m（2）的单个单元到（3 × 3）mm（2）芯片上的12，000个六边形单元不等。MOSFET特性表明，通过增加具有减小的单元间距的单元数量，大于100 A的电流对于6001- 1，200 V的阻断电压是现实的。阻断电压能力与可证明的高电流容量相结合表明，3C-SiC非常适合用于高功率和中等功率电子应用的垂直MOSFET。(C)2008 WILEY-VCH Verlag GmbH & Co. KGaA，魏因海姆。
The planar defect density of 3C-SiC can be reduced by growing it on undulant-Si substrates. However, specific stacking faults (SFs) remain, that expose the Si-face on the (001) surface. These residual SFs increase the leakage current in devices made with 3C-SiC. They can be eliminated using an advanced SF-reduction method called switch-back epitaxy (SBE) that combines polarity conversion with homoepitaxial growth. Vertical metal-oxide-semiconductor field-effect-transistors (MOSFETs) are fabricated on 3C-SiC with SBE, varying in size from a single cell with an area of (30 x 30) mu m(2) to 12,000 hexagonal cells on a (3 x 3) mm(2) chip. The MOSFET characteristics suggest that currents greater than 100 A are realistic for blocking voltages of 6001-1,200 V by increasing the number of cells with reduced cell-pitch. The combination of blocking voltage capability with a demonstrable high current capacity shows that 3C-SiC is well-suited for use in vertical MOSFETs for high- and medium-power electronic applications. (C) 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.