An area-efficient, pulse-based interconnect
An area-efficient, pulse-based interconnect
复制标题
面积高效、基于脉冲的互连
DOI：
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发表时间：
2006
期刊：
影响因子：
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通讯作者：
S. Moore
中科院分区：
文献类型：
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作者：
S. Hollis;S. Moore
We present a new style of long-distance, on-chip interconnects based loosely on the asynchronous GasP architecture, with a number of advantages over conventional interconnect. Most significant are a low wire count, a low area requirement, the absence of a global clock and simple composition with existing designs. We give some sample throughput and latency figures from simulation on a 0.18 mum technology, and show that it is viable for use with modern interconnect requirements, is of low complexity, and has a lower area requirement than parallel interconnect over distances as short as 1 mm
