Architecture for complex network measures of brain connectivity
Architecture for complex network measures of brain connectivity
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DOI：
10.1109/iscas.2017.8050239
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发表时间：
2017-05
期刊：
影响因子：
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通讯作者：
Chandrajit Pal;Dwaipayan Biswas;K. Maharatna;A. Chakrabarti
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文献类型：
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作者：
Chandrajit Pal;Dwaipayan Biswas;K. Maharatna;A. Chakrabarti
认知和运动障碍是日益增长的社会经济问题，其中药物治疗虽然是第一线行动，但并不总是有效地恢复认知和运动功能。研究表明，功能性大脑连接，即不同大脑区域之间的信息交换，与认知和运动任务的有效执行相关。因此，为了实时分析连接性参数以用于自动化疾病预后和控制，需要可以集成在感测设备内的优化的加速器/硬件设计。在这里，我们已经设计并实现了一个优化的硬件架构的图论参数（同时计算）的临床意义的功能连接性测量（相位滞后指数）的人脑网络。据我们所知，这是第一次研究大脑连接测量的复杂网络拓扑参数的实现，该参数已在25 Mhz合成，使用STMicroelectronics 130 nm技术库，动态功耗为10 nW，使其适合实时高速操作。
Cognitive and motor disorders are growing socio-economic concerns where drug treatments although being the first line of action, are not always effective in restoring cognitive and motor functionality. Research has shown that functional brain connectivity, signifying information exchange among different brain regions, is correlated with efficient execution of cognitive and motor tasks. Hence, to analyze the connectivity parameters in real-time for automated disease prognosis and control, an optimized accelerator/hardware design is required which can be integrated within the sensing device. Here we have designed and implemented an optimized hardware architecture of the graph theoretic parameters (computed concurrently) for the clinically significant functional connectivity measure (Phase Lag Index) of human brain network. To the best of our knowledge, this is a first study on the implementation of the complex network topology parameters of brain connectivity measure which has been synthesized at 25 Mhz, using STMicroelectronics 130-nm technology library and having a dynamic power consumption of 10 nW, making it amenable for real-time high speed operations.