Implementation of a low power 128-point FFT
Implementation of a low power 128-point FFT
复制标题
低功耗 128 点 FFT 的实现
DOI：
10.1109/icsict.1998.785898
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发表时间：
1998
期刊：
影响因子：
--
通讯作者：
H. Tenhunen
中科院分区：
文献类型：
--
作者：
Lihong Jia;Bingxin Li;Yonghong Gao;H. Tenhunen
本文基于我们提出的面向VLSI的快速傅里叶变换（FFT）算法基2/4/8，实现了一个低功耗的128点FFT处理器。片内存储器的新管理进一步降低了其功耗。该FFT处理器采用0.6 μ/m3.3V三层金属CMOS工艺设计，面积为10 mm/sup 2/.该芯片能够以3 /spl μ/s的速度计算128点FFT，在50 MHz输入频率下功耗为400 mW。
In this paper a low power 128 point fast Fourier transform (FFT) processor is implemented based on our new VLSI-oriented FFT algorithm-radix-2/4/8, which can effectively minimize the number of complex multiplications. A new management of the on-chip memory further reduce its power consumption. This FFT processor has been designed in 0.6 /spl mu/m 3.3 V triple-metal CMOS process with an area of 10 mm/sup 2/. The chip is capable of computing a 128 point FFT every 3 /spl mu/s and the power dissipation is 400 mW at 50 MHz input frequency.