A Generic Network Interface Architecture for a Networked Processor Array (NePA)
A Generic Network Interface Architecture for a Networked Processor Array (NePA)
复制标题
网络处理器阵列 (NePA) 的通用网络接口架构
DOI：
10.1007/978-3-540-78153-0_19
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
N. Bagherzadeh
中科院分区：
文献类型：
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作者：
Seung Eun Lee;J. Bahn;Yoon Seok Yang;N. Bagherzadeh
近年来，片上网络（NoC）技术作为一种很有前途的片上互连网络解决方案被提出。然而，集成组件的不同接口规范给采用NoC技术带来了相当大的困难。在本文中，我们提出了网络接口（NI）的通用架构和网络处理器阵列（基于NoC的多处理器SoC）的相关包装器，以便允许系统的设计流程来加速设计周期。存储器和涡轮解码器ip的案例研究表明了我们方法的可行性和有效性。
Recently Network-on-Chip (NoC) technique has been proposed as a promising solution for on-chip interconnection network. However, different interface specification of integrated components raises a considerable difficulty for adopting NoC techniques. In this paper, we present a generic architecture for network interface (NI) and associated wrappers for a networked processor array (NoC based multiprocessor SoC) in order to allow systematic design flow for accelerating the design cycle. Case studies for memory and turbo decoder IPs show the feasibility and efficiency of our approach.