Quasi-delay-insensitive compiler: Automatic synthesis of asynchronous circuits from verilog specifications
Quasi-delay-insensitive compiler: Automatic synthesis of asynchronous circuits from verilog specifications
复制标题
准延迟不敏感编译器：根据verilog规范自动合成异步电路
DOI：
10.1109/mwscas.2011.6026577
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发表时间：
2011
期刊：
影响因子：
--
通讯作者：
J. Chang
中科院分区：
文献类型：
--
作者：
Rong Zhou;Kwen;B. Gwee;J. Chang
在本文中，我们提出了一个编译器（EDA工具），自动综合异步准延迟不敏感的QDI）电路从Verilog HDL规范。该编译器接收Verilog HDL规范与标准的编码风格作为输入进行预处理，并生成组合逻辑和流水线框架。然后，组合逻辑可以通过商业EDA工具进行综合，随后，扩展为具有目标库单元的双轨电路。在这个建议的编译器四个显着有趣的功能如下。首先，所得到的电路是可以适应PVT变化的QDI电路。第二，编译器接受标准的同步电路规范，而不需要考虑特殊的设计规则。第三，该编译器采用了数据驱动的流水线，通过直接配置流水线框架避免了控制器综合。第四，该编译器可以使用不同的定制库单元将单轨电路转换为双轨电路。因此，这些库单元的充分优势可以用于不同的要求/应用。为了验证该编译器的有效性和实用性，给出了6个基于差分共源共栅电压摆幅逻辑（DCVSL）和空约定逻辑（NCL）库单元的电路实例，并给出了仿真结果。我们表明，我们提出的编译器具有更好的设计友好性，并提供了更大的设计灵活性。
In this paper, we present a compiler (EDA tool) that automatically synthesizes asynchronous Quasi-Delay-Insensitive QDI) circuits from Verilog HDL specification. The proposed compiler receives Verilog HDL specification with standard coding style as input for preprocessing, and generates combinational logics and pipeline frameworks. The combinational logics can then be synthesized by commercial EDA tools, subsequently, expanded into dual-rail circuits with target library cells. Four notably interesting features in this proposed compiler are as follows. First, the resulting circuits are QDI circuits which can accommodate PVT variations. Second, the compiler accepts standard synchronous circuit specification with no special design rules to be considered. Third, this compiler adopts a data-driven pipeline, avoiding controller synthesis by configuring pipeline framework directly. Fourth, this compiler can convert single-rail to dual-rail circuits with different customized library cells. Hence, full advantage of these library cells can be taken for different requirements/applications. To demonstrate the validity and practicality of this compiler, six circuit examples based on Differential Cascode Voltage Swing Logic (DCVSL) and NULL Convention Logic (NCL) library cells are presented with simulation results. We show that our proposed compiler features better design friendliness and provides greater design flexibility.