Real-time field programmable gate array architecture for computer vision
Real-time field programmable gate array architecture for computer vision
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DOI：
10.1117/1.1329341
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发表时间：
2001-01-01
影响因子：
1.1
通讯作者：
Torres-Huitzil, C
中科院分区：
文献类型：
--
作者：
Arias-Estrada, M;Torres-Huitzil, C
本文提出了一种掩模和图像的实时通用卷积架构。该架构旨在用于快速低级图像处理。基于现场可编程门阵列 (FPGA) 的架构利用 FPGA 中寄存器的可用性来实现高效且紧凑的模块来处理卷积。该架构旨在最大限度地减少对图像存储器的访问次数，并且基于具有内部流水线操作的并行模块，以提高其性能。该架构在 FPGA 中进行原型设计，但可以在专用的超大规模集成器件上实现，以达到更高的时钟频率。讨论了复杂性问题、FPGA 资源利用率、FPGA 限制和实时性能。一些结果被提出并讨论。 (C) 2001 SPIE 和 IS&T。
This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with infernal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but if can be implemented on dedicated very-large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed. (C) 2001 SPIE and IS&T.