Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools
Pulsar: Constraining QDI Circuits Cycle Time Using Traditional EDA Tools
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Pulsar：使用传统 EDA 工具限制 QDI 电路周期时间
DOI：
10.1109/async.2019.00023
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Ney Laert Vilar Calazans
中科院分区：
文献类型：
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作者：
M. Sartori;Rodrigo N. Wuerdig;Matheus T. Moreira;Ney Laert Vilar Calazans
异步准延迟不敏感（QDI）电路是已知的，其潜在的增强鲁棒性PVT变化相比，同步电路或捆绑数据异步设计。它们也是用于解决多个实际问题的高性能电路的理想选择。然而，通常难以约束QDI电路的最低性能。因此，提高QDI设计的综合质量是一项合理的努力，特别是在物联网和人工智能等新兴应用领域。这项工作提出了脉冲星，SDDS-NCL，以前提出的异步QDI模板和设计流程的扩展的基础上的方法。Pulsar带来了四个原创性的贡献：（i）两个新的模型，用于元件作为顺序的障碍;（ii）一个新的模型，半缓冲管道，半缓冲通道网络（HBCN）;（iii）一个线性规划公式，以定义一个电路的周期时间约束;（iv）一个设计流程，使自动化的过程中设计顺序SDDS-NCL电路。与Pulsar的6级乘-累加（MAC）电路的综合结果比较表明，该电路可以保证最大周期时间为3.2ns，而未进行逻辑优化的原始Unclesynthesised电路在6 ns约束下会导致时序违规。
Asynchronous quasi-delay-insensitive (QDI) circuits are known for their potentially enhanced robustness to PVT variations when compared to synchronous circuits or to bundled data asynchronous design. They are also a good choice for high performance circuits used to solve several real-world problems. However, it is often difficult to constrain the minimum performance for QDI circuits. Thus, enhancing the synthesis quality for QDI design is a justifiable effort, especially in rising application fields, such as the Internet of Things and Artificial Intelligence. This work proposes Pulsar, a method based on the extension of SDDS-NCL, a previously proposed asynchronous QDI template and design flow. Pulsar brings four original contributions: (i) two new models for components used to as sequential barriers; (ii) a new model for half buffer pipelines, half-buffer channel network (HBCN); (iii) a linear programming formulation to define a circuit cycle time constraint; (iv) a design flow that enables automating the process to design sequential SDDS-NCL circuits. Experiments comparing synthesis results with Pulsar of a 6-stage, multiply-accumulate (MAC) show that it can guarantee a maximum cycle time of 3.2ns, while the original Unclesynthesised circuit without logic optimisation leads to timing violations at a 6ns constraint.