A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing
A 5500-frames/s 85-GOPS/W 3-D Stacked BSI Vision Chip Based on Parallel In-Focal-Plane Acquisition and Processing
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DOI：
10.1109/jssc.2018.2886325
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发表时间：
2019-04-01
影响因子：
5.4
通讯作者：
Duranton, Marc
中科院分区：
文献类型：
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作者：
Millet, Laurent;Chevobbe, Stephane;Duranton, Marc
本文提出了一种 3D 堆叠视觉芯片，具有焦平面内读出功能，与灵活的计算架构紧密结合，可进行可配置的高速图像分析。该芯片架构基于可扩展的独立结构，集成了顶层的图像传感器和底层的处理元件（PE）和存储器。通过使用 3D 堆叠分区，我们的原型受益于背面照明像素灵敏度、图像传感器和 PE 之间的完全并行通信以实现低延迟性能，同时在底层留出足够的空间来嵌入高级计算功能。一种可扩展结构嵌入 16x16 像素阵列（或高分辨率模式下的 64 x 64 像素），与 8 位单指令多数据 (SIMD) 处理器相关联；采用双 130 nm 1P6M CMOS 工艺制造。本文展示了低分辨率模式下的 5500 帧/秒和每秒 85 千兆操作 (GOPS)/W，通过八方向像素间通信具有大内核功能。多流功能也被证明可以在视觉芯片的不同区域执行不同的程序。
This paper presents a 3-D stacked vision chip featuring in-focal-plane read-out tightly coupled with flexible computing architecture for configurable high-speed image analysis. The chip architecture is based on a scalable standalone structure integrating image sensor on the top tier and processing elements (PEs) plus memories in the bottom tier. By using 3-D stacking partitioning, our prototype benefits from backside illuminated pixels sensitivity, a fully parallel communication between image sensor and PEs for low-latency performances, while leaving enough room in the bottom tier to embed advanced computing features. One scalable structure embeds a 16x16 pixel array (or 64 x 64 pixels in high-resolution mode), associated with an 8-bit single instruction multiple data (SIMD) processor; fabricated in dual 130-nm 1P6M CMOS process. This paper exhibits a 5500 frames/s and 85 giga operations per second (GOPS)/W in low-resolution mode, with large kernels capabilities through eight directions interpixel communication. Multiflow capability is also demonstrated to execute different programs in different areas of the vision chip.