A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW
A 72dB-DR ΔΣ CT modulator using digitally estimated auxiliary DAC linearization achieving 88fJ/conv in a 25MHz BW
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72dB-DR ΔΣ CT 调制器使用数字估计辅助 DAC 线性化，在 25MHz 带宽下实现 88fJ/conv
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发表时间：
2012
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通讯作者：
M. Ortmanns
中科院分区：
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作者：
Pascal Witte;John G. Kauffman;J. Becker;Y. Manoli;M. Ortmanns
宽带、节能的连续时间ΔΣ调制器的持续趋势导致了各种实现，它们通常共享多比特量化、低过采样比和三阶或四阶环路滤波器的使用[1,2]。为了提高功率效率，电路和架构的创新[1]，以及数字实现[3]或数字校正模拟电路部分已被采用。迄今为止，带宽高于10MHz的ΔΣ调制器的最佳功率与性能比是由FoM为120fJ/conv的[1]保持的。
The ongoing trend for wide-band, power-efficient continuous-time ΔΣ modulators has led to various implementations, which commonly share the usage of multi-bit quantization, low oversampling ratio and 3rd or 4th-order loop-filters [1,2]. In order to improve power efficiency, circuit and architectural innovations [1], as well as digital implementation [3] or digital correction of analog circuit parts have been used. To date, the best power vs. performance ratio for ΔΣ modulators with above 10MHz bandwidth is held by [1] with an FoM of 120fJ/conv.