The Time Dilation Technique for Timing Error Tolerance
The Time Dilation Technique for Timing Error Tolerance
复制标题
时序误差容限的时间膨胀技术
DOI：
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发表时间：
2014
影响因子：
3.7
通讯作者：
X. Kavousianos
中科院分区：
文献类型：
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作者：
Stefanos Valadimas;A. Floros;Y. Tsiatouhas;A. Arapoyanni;X. Kavousianos
在纳米工艺集成电路中，时间误差容限是非常重要的。在本文中，时间膨胀设计技术，提出了提供并发错误检测和纠正的应用领域，也支持离线制造扫描测试。通过利用一个新的扫描触发器，时间膨胀技术是能够检测和纠正多个错误在一个时钟周期延迟的最小惩罚。与Razor设计方法相比，硅面积开销和功耗显著降低，因为不需要额外的存储器元件。同时，所提出的技术只引入了可忽略的性能下降，因为没有额外的电路被插入在设计的关键路径。
Timing error tolerance is of great importance in nanometer technology integrated circuits. In this paper, the Time Dilation design technique is proposed that provides concurrent error detection and correction in the field of application and also supports off-line manufacturing scan testing. By utilizing a new scan Flip-Flop, the Time Dilation technique is capable to detect and correct multiple errors at the minimum penalty of one clock cycle delay. The silicon area overhead and the power consumption are substantially reduced, as compared to the Razor design approach, since no additional memory elements are required. At the same time, the proposed technique introduces only negligible performance degradation since no extra circuitry is inserted in the critical paths of a design.