Reconfigurable parallel VLSI processor for dynamic control of intelligent robots
Reconfigurable parallel VLSI processor for dynamic control of intelligent robots
复制标题
用于智能机器人动态控制的可重构并行VLSI处理器
DOI：
10.1049/ip-cdt:19960103
复制
发表时间：
1996
期刊：
影响因子：
--
通讯作者：
N. Tomabechi
中科院分区：
文献类型：
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作者：
Y. Fujioka;M. Kameyama;N. Tomabechi
在智能机器人的传感器反馈控制中，对于大量的乘加运算，必须减小延迟时间。为了减少多操作数乘加运算的延迟时间，提出了一种可重构并行处理器的结构。在每个PE中，开关电路（SC）用于改变乘法器和加法器之间的连接。通过使用超长字（VLIW）控制方法改变SC中的开关元件，可以在每个时钟周期重新配置具有期望数量的乘法器的乘法器-加法器。由于数据传输是由乘法器和加法器之间的直接连接，数据传输的开销大大减少。此外，乘法器和加法器的利用率增加。基于0.8 /spl mu/m CMOS设计规则的芯片评估表明，用于七自由度（DOF）冗余机器人操作器的动态控制的延迟时间变为约10 /spl mu/s，这比使用常规数字信号处理器（DSP）的并行处理器方法快约7.7倍。
In the sensor feedback control of intelligent robots, the delay time must be reduced for a large number of multiply-additions. To reduce the delay time for multi-operand multiply additions, the architecture of the reconfigurable parallel processor is proposed. In each PE, a switch circuit (SC) is used to change the connection between multipliers and adders. By changing the switch elements in the SC using the very-long-instruction-word (VLIW) control method, the multiply-adders having desired numbers of multipliers can be reconfigured every clock cycle. Since the data transfer is performed by the direct connection between multipliers and adders, the overhead for data transfer is greatly reduced. In addition, the utilised ratio of the multipliers and the adders is increased. The chip evaluation based on 0.8 /spl mu/m CMOS design rule shows that the delay time for dynamic control of a seven-degrees-of-freedom (DOF) redundant robot manipulator becomes about 10 /spl mu/s which is about 7.7 times faster than that of a parallel-processor approach using conventional digital signal processors (DSPs).