A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC
A 65-fJ/conversion-step 0.9-V 200-kS/s rail-to-rail 8-bit successive approximation ADC
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DOI：
10.1109/jssc.2007.905237
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发表时间：
2007-10-01
影响因子：
5.4
通讯作者：
Lee, Guo-Ming
中科院分区：
文献类型：
--
作者：
Hong, Hao-Chiao;Lee, Guo-Ming
介绍了一种适用于能量受限应用的0.18 μ m CMOS 8位逐次逼近型模数转换器（SA ADC）。SA ADC仅采用一个自举开关，即可实现宽有效分辨率带宽（ERBW），从而保持所需的低功耗特性。测试结果表明，在0.9 V电源电压和200 kS/s输出速率下，SA ADC的峰值信噪比为47.4 dB，有效带宽可达100 kHz。它消耗2.47 μ W在测试中，对应于65 fJ/转换步骤的品质因数。
An 8-bit successive approximation (SA) analog-to-digital converter (ADC) in 0.18 mu m CMOS dedicated for energy-limited applications is presented. The SA ADC achieves a wide effective resolution bandwidth (ERBW) by applying only one bootstrapped switch, thereby preserving the desired low power characteristic. Measurement results show that at a supply voltage of 0.9 V and an output rate of 200 kS/s, the SA ADC performs a peak signal-to-noise-and-distortion ratio of 47.4 dB and an ERBW up to its Nyquist bandwidth (100 kHz). It consumes 2.47 mu W in the test, corresponding to a figure of merit of 65 fJ/conversion-step.