The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems

The Role of CAD Frameworks in Heterogeneous FPGA-Based Cloud Systems
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CAD 框架在基于 FPGA 的异构云系统中的作用

DOI:
10.1109/iccd.2017.74
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发表时间:
2017
期刊:
2017 IEEE International Conference on Computer Design (ICCD)
影响因子:
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通讯作者:
M. Santambrogio
M. Santambrogio
中科院分区:
--
文献类型:
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作者:
Lorenzo Di Tucci;Marco Rabozzi;Luca Stornaiuolo;M. Santambrogio

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在异性计算的背景下,尽管GPU是选举的组成部分,但由于其本质上平行的性质及其灵活性,FPGA也因选定的工作负载的较高功率而进行了研究和实验,而GPU是由于GPU所致,而GPU是由于选举的异质组成部分而导致的选举。由于所选工作负载上的较高功率效率,正在研究和试验它们的本质平行性和灵活性。但是,缺乏足够的语言,运行时间,编程灵活性以及广义上讲,用于FPGA加速应用的已验证的系统级方法是将这些设备采用到主流中的最相关的限制因素。在这些方面,亚马逊最近发布了Amazon Web Services(AWS)EC2 F1,它是配备Xilinx FPGA板的计算实例。在这种情况下,由于Xilinx称为SDACCEL的新软件,用户可以开发算法并在FPGA上运行它们。在本文中,我们描述了如何扩展CAOS框架与SDACCEL集成并通过FPGA加速度来提高自定义应用程序的性能。然后,我们提出了一项案例研究,以基于N​​体模拟问题来测试新方法。结果表明,我们能够实现与不到一天的工作中专家用户获得的绩效。
In the context of heterogneous computing, even though GPUs are the components of election due to both their intrinsically parallel nature and their flexibility, FPGAs are being investigated and experimented due to superior power efficiency on selected workloads While GPUs are the heterogeneous components of election due to both their intrinsically parallel nature and their flexibility, FPGAs are being investigated and experimented due to superior power efficiency on selected workloads. However, the lack of adequate languages, runtimes, programming flexibility and, broadly speaking, proven system level approaches for FPGA-accelerated applications are the most relevant limiting factors to the adoption of these devices into mainstream. In these regards, Amazon recently released Amazon Web Services (AWS) EC2 F1, which are compute instances that are equipped with Xilinx FPGA boards. On such instances, the user can develop algorithms and run them on FPGAs thanks to the new software developed by Xilinx called SDAccel. In this paper, we describe how we extended the CAOS framework to integrate with SDAccel and target AWS F1 instances for improving the performance of a custom application by means of FPGA acceleration. We then propose a case study to test the new methodology, based on the N-Body Simulation problem. Results show that we were able to achieve performance comparable to the ones obtained by expert users in less than a day of work.