A Practical Phase Gate for Producing Bell Violations in Majorana Wires
A Practical Phase Gate for Producing Bell Violations in Majorana Wires
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DOI：
10.1103/physrevx.6.021005
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发表时间：
2016-04-08
影响因子：
12.5
通讯作者：
Das Sarma, Sankar
中科院分区：
文献类型：
--
作者：
Clarke, David J.;Sau, Jay D.;Das Sarma, Sankar
利用非阿贝尔任意子（如Majorana零模式）进行容错拓扑量子计算是目前世界范围内实验努力的一个重要目标。然而，Gottesman-Knill定理[1]认为，如果一个系统除了在计算基中准备和检测量子位态之外，还只能执行可用量子操作的某个子集（即Clifford群的操作），则该系统不足以进行通用量子计算。事实上，在这样一个系统中，任何测量结果都可以在局部隐变量理论中重现，因此不需要量子力学解释，因此不可能有量子加速。不幸的是，Clifford运算恰恰是在支持非阿贝尔马约拉纳零模式的系统中通过编织和测量得到的运算，而非阿贝尔马约拉纳零模式则是拓扑保护量子计算的绝佳候选。为了超越经典可模拟的子空间，需要一个额外的相位门。该相位门允许系统违反约束局部隐变量理论的钟状clauser - horn - shimony - holt （CHSH）不等式。在本文中，我们为已经存在的基于半导体的马约拉纳线系统介绍了一种新型相门，并演示了如何使用CHSH测量对这种相门进行基准测试。我们提出了一个实验上可行的示意图，使用“仅测量”的方法，绕过了明确的马约拉纳编织的需要。这种方法可以扩展到超出违反CHSH所需的双量子位系统，从而导致使用Majorana零模式的通用容错量子计算的定义良好的平台。
Carrying out fault-tolerant topological quantum computation using non-Abelian anyons (e.g., Majorana zero modes) is currently an important goal of worldwide experimental efforts. However, the Gottesman-Knill theorem [1] holds that if a system can only perform a certain subset of available quantum operations (i.e., operations from the Clifford group) in addition to the preparation and detection of qubit states in the computational basis, then that system is insufficient for universal quantum computation. Indeed, any measurement results in such a system could be reproduced within a local hidden variable theory, so there is no need for a quantum-mechanical explanation and therefore no possibility of quantum speedup [2]. Unfortunately, Clifford operations are precisely the ones available through braiding and measurement in systems supporting non-Abelian Majorana zero modes, which are otherwise an excellent candidate for topologically protected quantum computation. In order to move beyond the classically simulable subspace, an additional phase gate is required. This phase gate allows the system to violate the Bell-like Clauser-Horne-Shimony-Holt (CHSH) inequality that would constrain a local hidden variable theory. In this article, we introduce a new type of phase gate for the already-existing semiconductor-based Majorana wire systems and demonstrate how this phase gate may be benchmarked using CHSH measurements. We present an experimentally feasible schematic for such an experiment using a "measurement-only" approach that bypasses the need for explicit Majorana braiding. This approach may be scaled beyond the two-qubit system necessary for CHSH violations, leading to a well-defined platform for universal fault-tolerant quantum computation using Majorana zero modes.