A novel scheme to reduce power supply noise for high-quality at-speed scan testing
A novel scheme to reduce power supply noise for high-quality at-speed scan testing
复制标题
DOI：
10.1109/test.2007.4437632
复制
发表时间：
2007-10
期刊：
影响因子：
--
通讯作者：
X. Wen;K. Miyase;S. Kajihara;Tatsuya Suzuki;Yuta Yamato;P. Girard;Yuji Ohsumi;Laung-Terng Wang
中科院分区：
文献类型：
--
作者：
X. Wen;K. Miyase;S. Kajihara;Tatsuya Suzuki;Yuta Yamato;P. Girard;Yuji Ohsumi;Laung-Terng Wang
高质量的全速扫描测试是实现DSM电路高延迟测试质量所必需的，其特点是具有高的小延迟缺陷检测能力。然而，由于高发射感应开关活动引起的电源噪声过大，这样的测试容易造成成品率损失。本文提出了一种新的实用的后ATPG X填充方案来解决这一严重问题，该方案包括：(1)一种称为路径保持X-识别的测试松弛方法，该方法从完全指定的转换延迟测试集中发现不关心的比特，同时通过保持最初对故障检测敏感的最长路径来保持其延迟测试质量；以及(2)一种称为调整概率填充(JP-Fill)的X填充方法，该方法对于减少发射引起的切换活动是有效且可扩展的。该方案可以很容易地在任何ATPG流程中实现，在不影响延迟测试质量、测试数据量、面积开销和电路时序的情况下，有效地降低电源噪声。
High-quality at-speed scan testing, characterized by high small-delay-defect detecting capability, is indispensable to achieve high delay test quality for DSM circuits. However, such testing is susceptible to yield loss due to excessive power supply noise caused by high launch-induced switching activity. This paper addresses this serious problem with a novel and practical post-ATPG X-filling scheme, featuring (1) a test relaxation method, called path keeping X-identification, that finds don't-care bits from a fully-specified transition delay test set while preserving its delay test quality by keeping the longest paths originally sensitized for fault detection, and (2) an X-filling method, called justification-probability-based fill (JP-fill), that is both effective and scalable for reducing launch-induced switching activity. This scheme can be easily implemented into any ATPG flow to effectively reduce power supply noise, without any impact on delay test quality, test data volume, area overhead, and circuit timing.