HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDL

HDLRuby: A Ruby Extension for Hardware Description and its Translation to Synthesizable Verilog HDL
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DOI:
10.1145/3581757
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发表时间:
2023-02
影响因子:
2
通讯作者:
Gauthier Lovic;Ishikawa Yohei
Gauthier Lovic;Ishikawa Yohei
中科院分区:
计算机科学3区
文献类型:
--
作者:
Gauthier Lovic;Ishikawa Yohei

文献摘要

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HDLRuby是一种新的硬件描述语言,它是Ruby编程语言的扩展,旨在提高电路设计的效率。HDLRuby允许在寄存器传输级对数字电路进行建模,同时支持包括面向对象编程、泛型、元编程和反射在内的高级范式。通过构造,HDLRuby还可以用Ruby执行任何代码,并支持Ruby的所有库。然而,即使高级功能有利于提高设计效率,如果设计工具的效率不足以生产出合理时间质量的硬件,那么这种优势也会被抵消。本文通过介绍用于编译HDLRuby描述和评估它们的性能的技术来研究这个问题。详细说明了该语言是如何实现的,以及如何将其转换为可合成的Verilog HDL。然后提出了实验,以确认使用HDLRuby的生产力增益,并评估翻译的性能,结果代码的大小,以及商用合成工具从它产生FPGA配置所需的时间。用于实验的HDLRuby描述包括一组用于单个构造评估的重复设计和用于实际应用的通用卷积神经网络的实现。在这些评价中,翻译时间比合成时间短10倍以上。
HDLRuby is a new hardware description language defined as an extension of the Ruby programming language aiming to improve circuit design productivity. HDLRuby allows to model digital circuits at the register transfer level while supporting high-level paradigms comprising object-oriented programming, genericity, metaprogramming, and reflection. By construction, HDLRuby can also execute any code in Ruby and supports all of its libraries. Yet, even if high-level features are beneficial for design productivity, such advantages can be negated if the design tools are not efficient enough for producing in reasonable time quality hardware. This paper investigates this issue by presenting the techniques used for compiling HDLRuby descriptions and by evaluating their performance. In detail, it explains how the language has been implemented and how it is translated to synthesizable Verilog HDL. Experiments are then presented for confirming the productivity gain of using HDLRuby and for evaluating the performance of the translation, the size of the resulting code, and the time required by a commercially available synthesis tool to produce an FPGA configuration from it. The HDLRuby descriptions used for the experiments include a set of repetitive designs for single construct evaluations and the implementation of generic convolution neural networks for real-life applications. For these evaluations, the translation time proves to be more than 10 times shorter than the synthesis time.