On Synthesis-for-Testability of Combinational Logic Circuits
On Synthesis-for-Testability of Combinational Logic Circuits
复制标题
组合逻辑电路的可综合测试性
DOI：
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发表时间：
1995
期刊：
影响因子：
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通讯作者：
S. Reddy
中科院分区：
文献类型：
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作者：
I. Pomeranz;S. Reddy
我们提出了一种综合方法，修改一个给定的电路，以减少电路中的门的数量和路径的数量。合成过程是基于替换子电路的给定电路的结构称为比较单元。比较单元可完全测试固定故障和路径延迟故障。此外，他们有少量的路径和门。这些性质使它们成为可测试电路合成的有效构建块。实验结果表明，减少了门和路径的数量，并增加了路径延迟故障的可测性。固定故障的随机模式可测性保持不变。
We propose a synthesis method that modifies a given circuit to reduce the number of gates and the number of paths in the circuit. The synthesis procedure is based on replacing subcircuits of the given circuit by structures called comparison units. Comparison units are fully testable for stuck-at faults and for path delay faults. In addition, they have small numbers of paths and gates. These properties make them effective building blocks for synthesis of testable circuits. Experimental results demonstrate reductions in the number of gates and paths and increased path delay fault testability. The random pattern testability for stuck-at faults remains unchanged.