Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching
Reducing the impact of intra-core process variability with criticality-based resource allocation and prefetching
复制标题
通过基于关键性的资源分配和预取来减少核心内流程可变性的影响
DOI：
10.1145/1366230.1366257
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发表时间：
2008
期刊：
影响因子：
--
通讯作者：
Daniel J. Sorin
中科院分区：
文献类型：
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作者：
Bogdan F. Romanescu;M. Bauer;S. Ozev;Daniel J. Sorin
我们开发架构技术来减轻过程可变性的影响。我们的技术隐藏的性能影响缓慢的组件，包括寄存器，功能单元，L1 I和L1 D缓存帧，而不减慢时钟频率或悲观地假设所有组件都很慢。利用以前为其他业务开发的想法-基于关键性的资源分配，预取和预取缓冲-我们允许设计工程师积极设置时钟频率，而无需担心无法满足此频率的组件子集。我们的技术优于速度分箱，因为时钟频率的好处超过了IPC的轻微损失。
We develop architectural techniques for mitigating the impact of process variability. Our techniques hide the performance effects of slow components-including registers, functional units, and L1I and L1D cache frames-without slowing the clock frequency or pessimistically assuming that all components are slow. Using ideas previously developed for other purposes-criticality-based allocation of resources, prefetching, and prefetch buffering-we allow design engineers to aggressively set the clock frequency without worrying about the subset of components that cannot meet this frequency. Our techniques outperform speed binning, because clock frequency benefits outweigh slight losses in IPC.