VLSI Architectures for 8 Bit Data Comparators for Rank Ordering Image Applications
VLSI Architectures for 8 Bit Data Comparators for Rank Ordering Image Applications
复制标题
用于排序图像应用的 8 位数据比较器的 VLSI 架构
DOI：
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
Malli karjuna
中科院分区：
文献类型：
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作者：
C. S. Babu;S. A. Reddy;Malli karjuna
所提出的工作的主要目标是开发一种新的数据比较器，它提供了一个经济的解决方案，排序/排序网络的速度，功率和面积的基础上。建议的工作包括六个不同的比较器的设计，用于8位比较。这六个不同的比较器的性能是针对XCV 1000 - 4 bg 560使用Xilinx 7.1i编译器工具，使用VHDL。结果发现，进位选择逻辑为基础的数据比较器需要更少的面积，适合于减少面积的应用。传统的基于逐位逻辑的数据比较器以较小的延迟操作。因此，该架构可用于高速应用。二进制补码使用二进制至超一位数据转换器，功耗更低。因此，基于二进制补码的实现适合于低功率实现。将不同的数据比较器结构应用于改进剪切排序的并行流水结构。这三种架构与其他现有的中位数发现架构进行了比较。结果表明，基于CSLA的并行结构、基于CBC的流水结构和基于2BEC的流水结构在面积、速度和功耗等方面均优于传统的中值搜索算法。
The main objective of the proposed work is to develop a new Data comparator which gives an economical solution for sorting / Rank ordering networks on the basis of speed, power, and area. The proposed work comprises a design of six different comparators for 8 -bit comparison. The performances of these six different comparators were targeted for XCV1000-4bg560 using Xilinx 7.1i compiler tool using VHDL. It was found that Carry select logic based data comparator requires less area and suitable for reduced area applications. The Conventional bit wise logic based data comparator operated with less delay. Hence this architecture can be used for high speed application. The Twos complement using binary to excess one data converter consumes less power. Hence a twos complement based implementation is suitable for low power implementations. The Different architecture for data comparators were applied on parallel and pipelined architecture of modified shear sorting. These three architectures were compared with other existing median finding architectures. It was found that the CSLA based parallel architecture, CBC based pipelined architecture and 2BEC based pipelined architecture were stand out in area, speed and power when compared with conventional median finding algorithms.