CMOS-based piezo-FET stress sensors in Wheatstone bridge configuration
CMOS-based piezo-FET stress sensors in Wheatstone bridge configuration
复制标题
采用惠斯通电桥配置的基于 CMOS 的压电 FET 应力传感器
DOI：
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发表时间：
2011
期刊：
影响因子：
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通讯作者：
O. Paul
中科院分区：
文献类型：
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作者：
P. Gieschke;B. Sbierski;O. Paul
本文报道了场效应晶体管（FET）为基础的应力传感器（压电场效应晶体管）的设计和表征。每个传感器由四个FET形成，连接为具有公共栅电极和合并的源极/漏极扩散的惠斯通电桥。传感器在强反转和饱和下工作，并提供与机械应力成比例的差分电压信号。最大应力灵敏度是通过使用NMOS器件用于σx′y′和PMOS器件用于（σx′x′-σy′y′）以及它们相对于晶轴的最佳取向来实现的。提出了针对低本征失调（设计A）、低功耗（设计B）和小尺寸（设计C）进行优化的三种设计。传感器采用商用0.35 µm CMOS技术制造。他们的灵敏度的特点是应用定义良好的正常和剪应力的四点弯曲桥和扭转桥，分别。从95个样品的晶圆探测器设置的共模和固有的偏移电压的变化，获得了统计上有意义的值。设计A的两个传感器的绝对灵敏度均为101 mV/MPa，所有失调电压的标准差均低于3 mV。
This paper reports on the design and characterization of field effect transistor (FET)-based stress sensors (piezo-FETs). Each sensor is formed by four FETs connected as a Wheatstone bridge with a common gate electrode and merged source/drain diffusions. The sensors are operated in strong inversion and saturation and provide a differential voltage signal proportional to mechanical stress. Maximal stress sensitivities are achieved by using NMOS devices for σx′y′ and PMOS devices for (σx′x′ − σy′y′) and by their optimal orientations with respect to the crystallographic axes. Three designs optimized for low intrinsic offset (design A), low power consumption (design B) and small size (design C) are presented. The sensors were fabricated in a commercial 0.35 µm CMOS technology. Their sensitivities were characterized by application of well-defined normal and shear stress on a four-point bending bridge and a torsional bridge, respectively. Statistically meaningful values of the common-mode and intrinsic offset voltage variations were obtained from 95 samples on a wafer prober setup. Absolute sensitivities of ≈1 mV/MPa are reported for both sensors of design A with standard deviations of all offset voltages below 3 mV.