Reliability evaluation of logic circuits using probabilistic gate models
Reliability evaluation of logic circuits using probabilistic gate models
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DOI:
10.1016/j.microrel.2010.07.154
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发表时间:
2011-02
期刊:
影响因子:
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通讯作者:
Jie Han;Hao Chen;E. Boykin;J. Fortes
中科院分区:
文献类型:
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作者:
Jie Han;Hao Chen;E. Boykin;J. Fortes