Scalable Quantum Error Correction for Surface Codes Using FPGA
Scalable Quantum Error Correction for Surface Codes Using FPGA
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DOI：
10.1109/qce57702.2023.00106
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发表时间：
2023-01
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通讯作者：
Namitha Liyanage;Yue Wu;Alexander Deters;Lin Zhong
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作者：
Namitha Liyanage;Yue Wu;Alexander Deters;Lin Zhong
容错量子计算机必须比错误出现的速度更快地解码和纠正错误。纠正错误的速度越快，计算机完成有用工作的时间就越多。并查 (UF) 解码器的平均时间复杂度略高于 $O(d^{3}$)。我们报告了 UF 解码器的分布式版本，它利用并行计算资源来进一步加速。使用基于 FPGA 的实现，我们凭经验证明，在给定 $O(d^{3}$ 并行计算资源的情况下，该分布式 UF 解码器相对于 $d$ 具有 $a$ 次线性平均时间复杂度。每个测量轮次的解码时间随着 $d$ 的增加而减少，这是量子误差的第一次该实现采用称为 Helios 的可扩展架构，将并行计算资源组织到混合树网格结构中，我们能够使用 Xilinx VCU129 FPGA 实现高达 21 的数据，在现象学噪声为 0.1% 的情况下，每轮测量的平均解码时间为 11.5 ns，明显快于任何现有的解码器实现，因为 Helios 的每轮解码时间随着 d 的增加而减少。任意大的$d$，且积压不增加。
A fault-tolerant quantum computer must decode and correct errors faster than they appear. The faster errors can be corrected, the more time the computer can do useful work. The Union-Find (UF) decoder is promising with an average time complexity slightly higher than $O(d^{3}$. We report a distributed version of the UF decoder that exploits parallel computing resources for further speedup. Using an FPGA-based implementation, we empirically show that this distributed UF decoder has $a$ sublinear average time complexity with regard to $d$ given $O(d^{3}$ parallel computing resources. The decoding time per measurement round decreases as $d$ increases, a first time for a quantum error decoder. The implementation employs a scalable architecture called Helios that organizes parallel computing resources into a hybrid tree-grid structure. We are able to implement $d$ up to 21 with a Xilinx VCU129 FPGA, for which an average decoding time is 11.5 ns per measurement round under phenomenological noise of 0.1 %, significantly faster than any existing decoder implementation. Since the decoding time per measurement round of Helios decreases with d, Helios can decode a surface code of arbitrarily large $d$ without a growing backlog.