IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs
IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs
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IEEE Std P1838：正在开发的 2.5D-、3D-和 5.5D-SIC 的 DfT 标准
DOI：
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发表时间：
2016
期刊：
影响因子：
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通讯作者：
Hailong Jiao
中科院分区：
文献类型：
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作者：
E. Marinissen;T. McLaurin;Hailong Jiao
对于堆叠式集成电路，有效的测试访问需要各个芯片中的可测试设计 (DfT) 功能以协调一致的方式运行，以通过堆叠将测试激励和响应从外部 I/O 向上或向下传输。如果堆栈中的所有芯片均由一家公司制造，则此 3D-DfT 可以是专有的。然而，在堆栈中的各种芯片可能来自不同公司的情况下，需要标准化 3D-DfT 来保证互操作性。 IEEE Std P1838 是一个正在开发的标准，专门解决了这个问题。本文介绍了 P1838 的状态报告，并描述了其三个主要硬件组件：串行控制机制、芯片包装寄存器和灵活的并行端口。
For stacked integrated circuits, effective test access requires the design-for-test (DfT) features in the various dies to operate in a concerted way to transport test stimuli and responses from and to the external I/Os up and down through the stack. This 3D-DfT can be proprietary if all dies in the stack are made by a single company. However, in the likely case that the various dies in the stack originate from different companies, standardized 3D-DfT is required to guarantee inter-operability. IEEE Std P1838 is a standard-under-development that addresses exactly this issue. This paper presents a status report of P1838 and describes its three main hardware components: a serial control mechanism, a die wrapper register, and a flexible parallel port.