How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning
How Good Is Your Verilog RTL Code?: A Quick Answer from Machine Learning
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DOI：
10.1145/3508352.3549375
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发表时间：
2022-10
期刊：
影响因子：
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通讯作者：
Prianka Sengupta;Aakash Tyagi;Yiran Chen;Jiangkun Hu
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文献类型：
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作者：
Prianka Sengupta;Aakash Tyagi;Yiran Chen;Jiangkun Hu
硬件描述语言（HDL）是设计数字电路的常用入口点。HDL编码风格和设计选择的差异可能会导致相当不同的设计质量和性能-功耗权衡。一般来说，HDL编码的影响在逻辑综合甚至布局完成之前并不清楚。然而，运行合成仅仅作为HDL代码的反馈在计算上是不经济的，特别是在早期设计阶段，当代码需要频繁修改时。此外，在设计收敛的后期阶段，高影响的工程变更单（ECO）负担，设计迭代变得过于昂贵。为此，我们提出了一种机器学习方法，以Verilog为基础的寄存器传输级（RTL）设计评估，而不通过合成过程。它将允许设计人员快速评估RTL设计的不同选项之间的性能-功耗权衡。实验结果表明，我们提出的技术实现了平均95%的预测准确率在放置后的分析，是6个数量级的速度比通过运行逻辑合成和布局评估。
Hardware Description Language (HDL) is a common entry point for designing digital circuits. Differences in HDL coding styles and design choices may lead to considerably different design quality and performance-power tradeoff. In general, the impact of HDL coding is not clear until logic synthesis or even layout is completed. However, running synthesis merely as a feedback for HDL code is computationally not economical especially in early design phases when the code needs to be frequently modified. Furthermore, in late stages of design convergence burdened with high-impact engineering change orders (ECO's), design iterations become prohibitively expensive. To this end, we propose a machine learning approach to Verilog-based Register-Transfer Level (RTL) design assessment without going through the synthesis process. It would allow designers to quickly evaluate the performance-power tradeoff among different options of RTL designs. Experimental results show that our proposed technique achieves an average of 95% prediction accuracy in terms of post-placement analysis, and is 6 orders of magnitude faster than evaluation by running logic synthesis and placement.