An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS
An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS
复制标题
1μm CMOS 中的 8-b 85-MS/s 并行流水线 A/D 转换器
DOI：
10.1109/4.210027
复制
发表时间：
1993
影响因子：
5.4
通讯作者：
P. Gray
中科院分区：
文献类型：
--
作者：
C. Conroy;D. Cline;P. Gray
提出了一种新的流水线模数转换器（ADC）的时间交错阵列结构。设计了一个由四个并联的开关电容（S/C）多级流水线ADC组成的原型。通过在阵列上共享电阻串、偏置电路和时钟生成电路，硬件成本被最小化。采用数字误差校正来降低比较器的精度要求。采用技术来最小化跨阵列的失配的影响。一个关键的电路问题是高速采样保持（S/H）放大器的设计：一个全差分，主要是NMOS，非折叠共源共栅运算放大器拓扑结构。实验芯片实现在1 μ m CMOS和8-B分辨率在85兆采样每秒（MS/s）的采样率获得。对于40 MHz的输入正弦波，信噪比加失真（S/（N+D））为41 dB。>
A new architecture consisting of a time-interleaved array of pipelined analog-to-digital converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Hardware cost is minimized by sharing resistor strings, bias circuitry and clock generation circuitry over the array. Digital error correction is employed to ease comparator accuracy requirements. Techniques are employed to minimize the effect of mismatches across the array. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier: a fully differential, mostly NMOS, non-folded-cascode operational-amplifier topology is used. An experimental chip was implemented in 1- mu m CMOS and 8-b resolution at a sample rate of 85 megasamples per second (MS/s) was obtained. Signal-to-noise plus distortion (S/(N+D)) was 41 dB for an input sinusoid of 40 MHz. >