Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor
Investigating the degradation behavior caused by charge trapping effect under DC and AC gate-bias stress for InGaZnO thin film transistor
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DOI：
10.1063/1.3609873
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发表时间：
2011-07-11
影响因子：
4
通讯作者：
Lin, Chia-Sheng
中科院分区：
文献类型：
--
作者：
Chen, Te-Chih;Chang, Ting-Chang;Lin, Chia-Sheng
本文研究了非晶态铟-镓-氧化锌薄膜晶体管在栅偏压下的退化机理。与直流工作相比，正交流栅压下的V-t漂移更大，这表明在交流脉冲周期的上升/下降过程中发生了额外的电子捕获机制。相反，在负栅偏应力作用下的退化行为表现出相反的退化趋势。由于电子陷阱和空穴陷阱分别是正负栅压和光照负栅偏压下的主要退化机制，因此在AC/DC工作下不同的退化趋势可以归因于电子和空穴陷阱效率的不同。(C)2011年美国物理研究所。[DOI：10.1063/1.3609873]
This letter investigates the degradation mechanism of amorphous indium-gallium-zinc oxide thin-film transistors under gate-bias stress. The larger V-t shift under positive AC gate-bias stress when compared to DC operation indicates that an extra electron trapping mechanism occurs during rising/falling time during the AC pulse period. In contrast, the degradation behavior under illuminated negative gate-bias stress exhibits the opposite degradation tendency. Since electron and hole trapping are the dominant degradation mechanisms under positive and illuminated negative gate-bias stress, respectively, the different degradation tendencies under AC/DC operation can be attributed to the different trapping efficiency of electrons and holes. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3609873]