NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis
NOCDEX: Network on Chip Design Space Exploration Through Direct Execution and Options Selection Through Principal Component Analysis
复制标题
NOCDEX：通过直接执行进行片上网络设计空间探索并通过主成分分析进行选项选择
DOI：
--
复制
发表时间：
2006
期刊：
影响因子：
--
通讯作者：
O. Hammami
中科院分区：
文献类型：
--
作者：
Xinyu Li;O. Hammami
片上系统（SoC）的设计越来越复杂。其中一个挑战是找出一个互连拓扑结构和一组架构参数，使面积和功耗最小，同时满足设计约束。本文的目的是提出一种新的设计空间探索方法的片上网络，使用（1）硬件仿真的快速性能评估，（2）实际的综合后的位置和路由的面积结果和（3）实际的最佳实施频率计算的执行时间，而不是周期数。基于这些值，基于主元分析的统计工具为片上网络设计人员带来了生产率的提高，从而快速选择片上网络组件的适当参数值。总的来说，本文介绍了全自动片上网络实现跨层分析的综合方式。案例研究验证了我们的方法。
The design of system on chip (SoC) is getting more and more complex. One of the challenges is to find out an interconnection topology and a set of architecture parameters which minimize the area and power consumption while satisfying design constraint. The object of this paper is to propose a new design space exploration methodology for network on chip which use (1) hardware emulation for fast performance evaluation (2) actual post synthesis place and route for area results and (3) actual optimal implementation frequency to compute execution time rather than number of cycles. Based on these values, a statistical tool based on principal component analysis brings productivity gains for network on chip designer to quickly select network on chip components appropriate parameters value. Generally speaking the paper introduces fully automatic network on chip implementation cross-layer analysis in an integrated manner. Case studies validate our approach.