Measurement and Simulation Methods for Assessing SRAM Reliability Against Random Telegraph Noise

Measurement and Simulation Methods for Assessing SRAM Reliability Against Random Telegraph Noise
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评估 SRAM 针对随机电报噪声可靠性的测量和仿真方法

DOI:
10.1007/978-3-030-37500-3_8
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发表时间:
2020
影响因子:
4
通讯作者:
K. Takeuchi
K. Takeuchi
中科院分区:
物理与天体物理2区
文献类型:
--
作者:
K. Takeuchi

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在这一章中,统计特性和估计的随机电报噪声(RTN)对静态随机存取存储器(SRAM)的可靠性的影响的方法进行了说明。RTN是指晶体管的两个导电状态之间随时间的随机转变,与单个电子或空穴的捕获/去捕获相关联。对于使用极小晶体管的先进集成电路来说,这是一个可靠性问题,因为它们的电特性可以仅由单个基本电荷载流子显著改变,这可能导致电路故障。使RTN表征困难的一件事是其统计性质,因为晶体管中现有的电荷陷阱数量以及与每个陷阱相关的信号幅度和时间常数都将从一个晶体管到另一个晶体管而变化。此外,时间常数分布在几个阶上,并且可能不可预测地长。为了解决这个问题,RTN的表征使用SRAM阵列,其中大量的SRAM故障事件RTN记录和统计分析。提出了一种快速蒙特卡罗模拟的方法,该方法可以方便地与SRAM的测试结合使用。由此获得的信息可用于正确设计SRAM单元,以及它们的出货测试,使得故障的概率被抑制到可接受的水平。
In this chapter, methods for statistically characterizing and estimating the impact of random telegraph noise (RTN) on static random access memory (SRAM) reliability are described. RTN refers to random transition between two conduction states of a transistor with time, associated with trapping/de-trapping of a single electron or hole. It is a reliability concern for advanced integrated circuits using extremely small transistors, since their electrical characteristics can be significantly altered by only a single elementary charge carrier, which may lead to circuit malfunction. One thing that makes RTN characterization difficult is its statistical nature, as both the existing number of charge traps in a transistor as well as signal amplitude and time constants associated with each trap will vary from one transistor to another. In addition, the time constants are distributed over several orders, and may be unpredictably long. To address this matter, RTN characterization using SRAM arrays was proposed, where a large number of SRAM malfunction events by RTN are recorded and statistically analyzed. A method of fast Monte Carlo simulation was also proposed, which can be conveniently used in combination with the SRAM measurements. The information thus obtained can be used to properly design SRAM cells, as well as their shipment tests, so that the probability of malfunction is suppressed to an acceptable level.