Room-temperature demonstration of low-voltage and tunable static memory based on negative differential conductance in silicon single-electron transistors
Room-temperature demonstration of low-voltage and tunable static memory based on negative differential conductance in silicon single-electron transistors
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DOI：
10.1063/1.1839643
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发表时间：
2004-12
影响因子：
4
通讯作者：
M. Saitoh;H. Harata;T. Hiramoto
中科院分区：
文献类型：
--
作者：
M. Saitoh;H. Harata;T. Hiramoto
提出了一种基于硅单电子晶体管负微分电导（NDC）的静态存储器。我们制作了一个室温（RT）工作的单孔晶体管（SHT），其形式为超箭头线沟道金属氧化物半导体场效应晶体管（MOSFET），并观察到由于在RT下超小点的大量子能级间距而产生的清晰的NDC。通过将显示NDC的SHT和作为负载的p型MOSFET串联在单个芯片上，在0.2V的电源电压下，在RT的栅控存储器的操作被证明。提出的存储器具有与现有的超大规模集成电路，紧凑的尺寸，低电压，和可调操作的高兼容性。
A static memory based on negative differential conductance (NDC) in silicon single-electron transistors is proposed. We fabricate a room-temperature (RT) operating single-hole transistor (SHT) in the form of an ultranarrow wire channel metal-oxide-semiconductor field-effect transistor (MOSFET), and observe clear NDC due to large quantum level spacing of an ultrasmall dot at RT. By serially connecting an SHT showing NDC and a p-type MOSFET acting as a load on a single chip, gate-controllable memory operation is demonstrated at the supply voltage of 0.2V at RT. The proposed memory features high compatibility with the existing very-large-scale integrated circuits, compact size, low-voltage, and tunable operation.