Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores
复制标题
内置自测试内核的片上系统的连续可测试性设计
DOI：
10.1023/a:1016553809732
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发表时间：
2002
期刊：
影响因子：
--
通讯作者：
H. Fujiwara
中科院分区：
文献类型：
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作者：
T. Yoneda;H. Fujiwara
本文引入了连续可测试性的概念，提出了一种基于整数线性规划问题的可测试性设计方法。对于连续可测试的SoC，可以如下执行测试。核心的测试模式以系统时钟的速度从测试模式源(片外或芯片上实现)连续地传播到核心输入。类似地，测试响应以系统时钟的速度从核心输出连续传播到测试响应接收器(片外或片上实现)。通过使用周围核心的互连和连续透明属性来实现测试图案和响应的传播。所有互连都可以用类似的方式进行测试。因此，不仅可以测试逻辑故障，而且可以测试需要以系统时钟的速度连续施加测试图案的时序故障，因为连续可测试的SoC可以实现以系统时钟的速度连续施加任何测试序列。
This paper introduces a new concept of testability called consecutive testability and proposes a design-for-testability method for making a given SoC consecutively testable based on integer linear programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from test pattern sources (implemented either off-chip or on-chip) consecutively at the speed of system clock. Similarly the test responses are propagated to test response sinks (implemented either off-chip or on-chip) from the core outputs consecutively at the speed of system clock. The propagation of test patterns and responses is achieved by using interconnects and consecutive transparency properties of surrounding cores. All interconnects can be tested in a similar fashion. Therefore, it is possible to test not only logic faults but also timing faults that require consecutive application of test patterns at the speed of system clock since the consecutively testable SoC can achieve consecutive application of any test sequence at the speed of system clock.