Associative Instruction Reordering to Alleviate Register Pressure
Associative Instruction Reordering to Alleviate Register Pressure
复制标题
关联指令重新排序以减轻寄存器压力
DOI：
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发表时间：
2018
期刊：
影响因子：
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通讯作者：
P. Sadayappan
中科院分区：
文献类型：
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作者：
P. Rawat;Aravind Sukumaran;A. Rountev;F. Rastello;L. Pouchet;P. Sadayappan;P. Sadayappan
注册分配通常被认为是实际解决的问题。对于大多数应用程序，生产编译器中的寄存器分配策略非常有效地控制负载/商店的数量和寄存器溢出。但是，现有的寄存器分配策略无效，并导致高度多到多个数据重用的计算模式过度溢出，例如，高阶模具和张量收缩。我们制定了一个来源指令重新排序策略，该策略利用了重新排序关联操作以减轻寄存器压力的灵活性。开发的转换模块实现了一种适应性的策略，该策略可以适当地控制教学水平并行性的程度，同时减轻寄存器压力。通过使用多个生产编译器（GCC，Clang/LLVM）和目标平台（Intel Xeon Phi和Intel X86多核）的实验结果证明了该方法的有效性。
Register allocation is generally considered a practically solved problem. For most applications, the register allocation strategies in production compilers are very effective in controlling the number of loads/stores and register spills. However, existing register allocation strategies are not effective and result in excessive register spilling for computation patterns with a high degree of many-to-many data reuse, e.g., high-order stencils and tensor contractions. We develop a source-to-source instruction reordering strategy that exploits the flexibility of reordering associative operations to alleviate register pressure. The developed transformation module implements an adaptable strategy that can appropriately control the degree of instruction- level parallelism, while relieving register pressure. The effectiveness of the approach is demonstrated through experimental results using multiple production compilers (GCC, Clang/LLVM) and target platforms (Intel Xeon Phi, and Intel x86 multi-core).