A parallel architecture for relaxation operations
A parallel architecture for relaxation operations
复制标题
松弛操作的并行架构
DOI：
10.1016/0031-3203(88)90025-8
复制
发表时间：
1988
影响因子：
8
通讯作者：
Hiromitsu Yamada
中科院分区：
文献类型：
--
作者：
M. Kamada;K. Toraichi;R. Mori;Kazuhiko Yamamoto;Hiromitsu Yamada
松弛方法作为图像处理和模式识别中有效的并行方法而受到关注。但他们以前的并行实现是专门针对每个应用程序的，例如像素级的图像处理。本文提出了一种可应用于一般用途的松弛处理器的并行架构。该架构基于处理元件之间数据通信的循环结构。通过评估其应用于模式识别方法时的性能来讨论其有效性。
Relaxation method attracts attention as an effective parallel method in image processing and pattern recognition. But their previous parallel implementations are specialized to each application such as image processing at pixel level. The present paper proposes a parallel architecture for a relaxation processor which can be applied to general use. This architecture is based on the round-robin structure of data communication among the processing elements. Its effectiveness is discussed by evaluating its performance when applied to a pattern recognition method.