A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS
A 0.6 V, 1.74 ps Resolution Capacitively Boosted Time-to-Digital Converter in 180 nm CMOS
复制标题
采用 180 nm CMOS 封装的 0.6 V、1.74 ps 分辨率电容升压时间数字转换器
DOI：
--
复制
发表时间：
2019
期刊：
影响因子：
--
通讯作者：
L. Siek
中科院分区：
文献类型：
--
作者：
A. R. Palaniappan;L. Siek
采用180 nm / 1.8 V CMOS工艺设计的新型游标延迟线时间数字转换器（TDC）能够在超低电源电压下实现超精细分辨率。所提出的TDC被命名为电容升压游标延迟线TDC（CB-VDL TDC），由使用电容升压延迟缓冲器构建的游标延迟线组成，能够放大高于电源和低于地的输入时间信号，以便即使在超低工作电源电压下也能以更高的强度驱动后续缓冲器。所提出的 6 位 CB-VDL TDC 在 0.6 V 超低电源下工作时实现了 1.74 ps 的超精细分辨率，在 50 MHz 采样频率下功耗为 217.43 μW，因此非常适合低功耗全数字锁相环、飞行时间测量系统和时间模式模数转换器等应用。 TDC 核心占地 1.225 mm2，包括 180 nm CMOS 中的片上校准单元。
A new vernier delay line time-to-digital converter (TDC) capable of achieving an ultra-fine resolution at an ultra-low supply voltage is designed in 180 nm / 1.8 V CMOS process. The proposed TDC named as capacitively boosted vernier delay line TDC (CB-VDL TDC) consists of a vernier delay line built using capacitive boosting delay buffers capable of amplifying the input time signals higher than the supply and below the ground for driving the subsequent buffers with improved strength even at an ultra-low operating supply voltage. The proposed 6-bit CB-VDL TDC achieves an ultra-fine resolution of 1.74 ps while operating at an ultra-low supply of 0.6 V and consumes a power of 217.43 μW at a sampling frequency of 50 MHz, thus making it highly suitable for applications such as low power all-digital phase locked loops, time-of-flight measurement systems and time-mode analog-to-digital converters. The TDC core occupies an area of 1.225 mm2 including the on-chip calibration unit in 180 nm CMOS.