An 8-bit 100-GS/s distributed DAC in 28-nm CMOS
An 8-bit 100-GS/s distributed DAC in 28-nm CMOS
复制标题
采用 28 nm CMOS 的 8 位 100 GS/s 分布式 DAC
DOI：
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发表时间：
2014
期刊：
影响因子：
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通讯作者：
M. Berroth
中科院分区：
文献类型：
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作者：
Hao Huang;Johannes Heilmeyer;M. Grozing;M. Berroth
介绍了一种采用28 nm低功耗CMOS工艺、采用分布式输出拓扑结构的8位100 GS/s数模转换器（DAC）。在100 GS/s时，从直流到24.9 GHz，有效位和无杂散动态范围分别为5.3位和41 dB至3.2位和27 dB。-3dB带宽大于10 GHz。100 GS/s DAC由两个50 GS/s时间交错子DAC组成，采用两个相移为90°的25 GHz时钟信号工作。由于这种结构，输出频率滚降与50 GS/s DAC相当，而输出频率镜像抑制与100 GS/s DAC相当，从而降低了输出频带利用率。利用1 kbyte片内存储器，DAC可以循环转换1 k个符号，这足以表征DAC的性能。DAC采用1.1V/1.5V/2 V电源供电时功耗为2.5 W。测试芯片的面积为1.5mm2。
An 8-bit 100-GS/s digital-to-analog converter (DAC) using a distributed output topology in 28-nm low-power CMOS is presented. The ENOB and SFDR ranges from 5.3 bit and 41 dB to 3.2 bit and 27 dB from DC up to 24.9 GHz at 100 GS/s. The -3dB bandwidth is larger than 10 GHz. The 100 GS/s DAC is composed of two 50 GS/s time-interleaved sub-DACs and is operated from two 25 GHz clock signals with a phase shift of 90°. Due to this structure, the output frequency roll-off is comparable to a 50 GS/s DAC while the output frequency image rejection is comparable to a 100 GS/s DAC, easing the output frequency band utilization. With 1-kbyte on-chip memory the DAC can convert 1k symbols cyclically, which is sufficient for characterizing the DAC performance. The DAC consumes 2.5 W from a 1.1V/1.5V/2V power supply. The area of the test chip is 1.5mm2.