ParTejas: A parallel simulator for multicore processors
ParTejas: A parallel simulator for multicore processors
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ParTejas：多核处理器的并行模拟器
DOI：
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发表时间：
2014
期刊：
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通讯作者：
S. Sarangi
中科院分区：
文献类型：
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作者：
Geetika Malhotra;Pooja Aggarwal;Abhishek Sagar;S. Sarangi
在本文中，我们提出了一种名为 ParTejas 的新型多核模拟器的设计。它是一个用 Java 编写的基于共享内存的快速并行模拟器。与最近发布的主要依赖于采样、高级模型和高度宽松的同步的并行模拟器不同，我们主要依赖于新颖的并发数据结构。具体来说，我们使用无锁并行槽调度程序来同步共享资源上多个线程的访问，并使用称为移相器的灵活屏障来放松边界内的同步。我们利用 Java 的其他语言特定功能，并在 Splash2 和 Parsec 基准测试套件中展示了 64 个线程的平均加速率为 11.8 倍（模拟速度为 4-8 MIPS）。
In this paper, we present the design of a novel multicore simulator called ParTejas. It is a fast shared memory based parallel simulator written in Java. Unlike recently released parallel simulators that mainly rely on sampling, high level models, and highly relaxed synchronization, we primarily rely on novel concurrent data structures. In specific, we use a lock free parallel slot scheduler for synchronizing the accesses of multiple threads at a shared resource, and we use flexible barriers known as phasers to relax synchronization within bounds. We leverage additional language specific features of Java, and demonstrate a mean speedup of 11.8X (simulation speed of 4-8 MIPS) with 64 threads for a suite of Splash2 and Parsec benchmarks.