Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping
Germanium p-Channel FinFET Fabricated by Aspect Ratio Trapping
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DOI：
10.1109/ted.2013.2295883
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发表时间：
2014-01
影响因子：
3.1
通讯作者：
M. V. van Dal;G. Vellianitis;B. Duriez;G. Doornbos;C. Hsieh;Bi-Hui Lee;K. Yin;M. Passlack;Carlos H. Díaz
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文献类型：
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作者：
M. V. van Dal;G. Vellianitis;B. Duriez;G. Doornbos;C. Hsieh;Bi-Hui Lee;K. Yin;M. Passlack;Carlos H. Díaz
我们报道了采用深宽比捕获技术在300 mm硅晶片上制作的Ge p沟道FinFET。对于长沟道器件，陷阱辅助隧穿和带到带隧穿泄漏机制的组合负责限制关断状态漏极电流的升高的体电流。然而，后者可以通过设备设计来减轻。在VDS=-0.5 V时，长沟道亚阈值摆幅低至76 mV/decade，短沟道效应控制良好，且具有高的介电常数（对于70 nm的LG，VDS=-1 V时gm=1.2 mS/μ m，VDS=-0.5 V时gm = 1.05 mS/μm）。本文中介绍的Ge FinFET表现出最高的gm/SSsat在VDD=1 V的非平面无应变Ge p-FET的报告日期。
We report scaled Ge p-channel FinFETs fabricated on a 300-mm Si wafer using the aspect-ratio-trapping technique. For long-channel devices, a combination of a trap-assisted tunneling and a band-to-band tunneling leakage mechanism is responsible for an elevated bulk current limiting the OFF-state drain current. However, the latter can be mitigated by device design. We report low long-channel subthreshold swing of 76 mV/decade at VDS=-0.5 V, good short-channel effect control, and high transconductance (gm=1.2 mS/μm at VDS=-1 V and 1.05 mS/μm at VDS=-0.5 V for LG=70 nm). The Ge FinFET presented in this paper exhibits the highest gm/SSsat at VDD=1 V reported for nonplanar unstrained Ge p-FETs to date.