MESA-SIDEWALL GATE LEAKAGE IN INALAS INGAAS HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS
MESA-SIDEWALL GATE LEAKAGE IN INALAS INGAAS HETEROSTRUCTURE FIELD-EFFECT TRANSISTORS
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DOI：
10.1109/16.155875
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发表时间：
1992-09-01
影响因子：
3.1
通讯作者：
DELALAMO, JA
中科院分区：
文献类型：
--
作者：
BAHL, SR;LEARY, MH;DELALAMO, JA
通过传统台面隔离制造的 InAlAs/InGaAs HFET 具有潜在的寄生栅极泄漏路径，其中栅极金属化与台面侧壁处暴露的沟道边缘重叠。我们通过制造具有不同台面侧壁栅极金属重叠长度的特殊异质结二极管，明确地证明了这条路径的存在。我们发现侧壁泄漏是侧壁晶体取向的函数，并且随着沟道厚度、侧壁重叠面积和沟道中 InAs 摩尔分数的增加而增加。在与二极管一起制造的 HFET 中，侧壁泄漏增加了亚阈值和正向栅极泄漏电流，并降低了击穿电压。
InAlAs/InGaAs HFET's fabricated by conventional mesa isolation have a potential parasitic gate-leakage path where the gate metallization overlaps the exposed channel edge at the mesa sidewall. We have unmistakably proven the existence of this path by fabricating special heterojunction diodes with different mesa-sidewall gate-metal overlap lengths. We find that sidewall leakage is a function of the crystallographic orientation of the sidewall, and increases with channel thickness, sidewall overlap area, and InAs mole fraction in the channel. In HFET's fabricated alongside the diodes, sidewall leakage increased the subthreshold and forward gate leakage currents, and reduced the breakdown voltage.