Control plane hardware design for optical packet switched data centre networks
Control plane hardware design for optical packet switched data centre networks
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发表时间：
2020-01
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通讯作者：
Paris Andreades
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作者：
Paris Andreades
数据中心内网络的光数据包交换是满足流量需求的关键。光子集成和波分复用 (WDM) 可以克服交换系统中的带宽限制。半导体光放大器 (SOA) 是构建与 WDM 兼容的纳秒级可重构光子集成开关的一项有前途的技术。 SOA 通常用作广播和选择中的门控元件（B\S），它应该在数据包时间尺度上运行，随着线路速率的提高，这变得越来越具有挑战性。用于分配交换机路径的调度程序限制了控制时钟速度。为此，研究贡献是为交叉开关和 Clos 网络交换机设计高度并行的硬件调度程序。在现场可编程门阵列 (FPGA) 上，实现的最小调度程序时钟周期为 5.0~ns 和 5.4~ns，对于通过使用并行路径分配模块，每个 Clos 节点可实现 7.0~ns 的最小时钟周期，对于调度器专用集成电路 (ASIC) 综合来说，这可减少至 2.0~ns；此外，还通过实验证明了控制平面的性能。对于 256 端口 Clos 交换机，流量负载为容量的 60%，数据包延迟为亚微秒，优于最先进的光数据包交换机。
Optical packet switching for intra-data centre networks is key to addressing traffic requirements. Photonic integration and wavelength division multiplexing (WDM) can overcome bandwidth limits in switching systems. A promising technology to build a nanosecond-reconfigurable photonic-integrated switch, compatible with WDM, is the semiconductor optical amplifier (SOA). SOAs are typically used as gating elements in a broadcast-and-select (B\S it should run on packet timescales, which becomes increasingly challenging as line rates get higher. The scheduler, used for the allocation of switch paths, limits control clock speed. To this end, the research contribution was the design of highly parallel hardware schedulers for crossbar and Clos network switches. On a field-programmable gate array (FPGA), the minimum scheduler clock period achieved was 5.0~ns and 5.4~ns, for a 32-port crossbar and Clos switch, respectively. By using parallel path allocation modules, one per Clos node, a minimum clock period of 7.0~ns was achieved, for a 256-port switch. For scheduler application-specific integrated circuit (ASIC) synthesis, this reduces to 2.0~ns; a record result enabling scalable packet switching. Furthermore, the control plane was demonstrated experimentally. Moreover, a cycle-accurate network emulator was developed to evaluate switch performance. Results showed a switch saturation throughput at a traffic load 60\% of capacity, with sub-microsecond packet latency, for a 256-port Clos switch, outperforming state-of-the-art optical packet switches.