Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs
Compact-2D: A Physical Design Methodology to Build Two-Tier Gate-Level 3-D ICs
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Compact-2D：构建两层门级 3D IC 的物理设计方法
DOI：
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发表时间：
2020
影响因子：
2.9
通讯作者：
S. Lim
中科院分区：
文献类型：
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作者：
B. W. Ku;Kyungwook Chang;S. Lim
晶片键合和单片集成技术的最新进展为面对面(F2F)和单片3-D(M3D)IC提供了细粒度3-D互连。在本文中，我们提出了一种全芯片RTL-to-GDSII物理设计方案，以构建商业质量的两层门级F2F和M3D IC。名为Srunk-2D(S2D)的最先进流程需要将标准单元和互连缩小50%，以适应两层设计的目标3-D占地面积。不幸的是，这需要商业布局/路线引擎来处理一个节点较小的几何图形，这可能是具有挑战性的和昂贵的。我们的名为COMPACT-2D(C2d)的流不需要任何几何收缩。取而代之的是，C2D实现了具有可缩放互连$RC$寄生的2-D IC，并将布局收缩到3-D集成电路面积。此外，C2d还提供S2D中完全缺少的层后分区优化(Post-TP OPT)。这一额外的优化步骤被证明在修复由层间3-D布线开销引起的时序冲突方面是有效的。最后，我们提出了一种方法来重用后TP OPT的路由结果用于最终的GDS II生成。实验结果表明，与商用2-D芯片相比，C2d在性能相同的情况下，在没有任何布线资源开销的情况下，功耗降低了28.0%，硅片面积节省了15.6%。
The recent advancement of wafer bonding and monolithic integration technology offers fine-grained 3-D interconnections to face-to-face (F2F) and monolithic 3-D (M3D) ICs. In this article, we propose a full-chip RTL-to-GDSII physical design solution to build commercial-quality two-tier gate-level F2F and M3D ICs. The state-of-the-art flow named shrunk-2D (S2D) requires shrinking of standard cells and interconnects by a factor of 50% to fit into the target 3-D footprint of a two-tier design. This, unfortunately, necessitates commercial place/route engines that handle one node smaller geometries, which can be challenging and costly. Our flow named compact-2D (C2D) does not require any geometry shrinking. Instead, C2D implements a 2-D IC with scaled interconnect $RC$ parasitics and contracts the layout to the 3-D integrated circuit footprint. In addition, C2D offers post-tier-partitioning optimization (post-TP opt) which is completely missing in S2D. This additional optimization step is shown to be effective in fixing timing violations caused by intertier 3-D routing overhead. Lastly, we present a methodology to reuse the routing result of post-TP opt for the final GDSII generation. Our experimental results show that at iso-performance, C2D offers up to 28.0% power reduction and 15.6% silicon area savings over commercial 2-D ICs without any routing resource overhead.