A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration
A low on-resistance triple RESURF SOI LDMOS with planar and trench gate integration
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具有平面和沟槽栅极集成的低导通电阻三重 RESURF SOI LDMOS
DOI：
10.1088/1674-1056/21/6/068501
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发表时间：
2012-06
影响因子：
1.7
通讯作者：
Wei Jie
中科院分区：
文献类型：
--
作者：
Wang Yuan-Gang;Lei Tian-Fei;Zhang Yun-Xuan;Wei Jie
提出了一种低导通电阻（Ron,sp）可集成绝缘体上硅（SOI）n沟道横向双扩散金属氧化物半导体（LDMOS），并通过仿真研究了其机理。 LDMOS有两个特点：平面栅极和延伸沟槽栅极（双栅极（DG））的集成；以及 N 漂移区中的埋入 P 层，形成三重减小表面场 (RESURF) (TR) 结构。三重RESURF不仅可以调节电场分布，还可以增加N漂移掺杂，从而降低比导通电阻(Ron,sp)并提高关断状态下的击穿电压(BV)。 DG形成双导通沟道，此外，延伸的沟槽栅极加宽了垂直导通面积，这两者都进一步降低了Ron,sp。通过仿真，DG TR 金属氧化物半导体场效应晶体管 (MOSFET) 的 BV 和 Ron,sp 分别为 328 V 和 8.8 m??cm2。与传统SOI LDMOS相比，具有与DG TR MOSFET相同尺寸器件参数的DG TR MOSFET可将Ron,Sp降低59%，将BV提高6%。延伸沟槽栅极同时充当高压集成电路中高压器件和低压电路之间的隔离沟槽，从而节省了芯片面积并简化了制造工艺。
A low on-resistance (Ron,sp) integrable silicon-on-insulator (SOI) n-channel lateral double-diffused metal-oxide-semiconductor (LDMOS) is proposed and its mechanism is investigated by simulation. The LDMOS has two features: the integration of a planar gate and an extended trench gate (double gates (DGs)); and a buried P-layer in the N-drift region, which forms a triple reduced surface field (RESURF) (TR) structure. The triple RESURF not only modulates the electric field distribution, but also increases N-drift doping, resulting in a reduced specific on-resistance (Ron,sp) and an improved breakdown voltage (BV) in the off-state. The DGs form dual conduction channels and, moreover, the extended trench gate widens the vertical conduction area, both of which further reduce the Ron,sp. The BV and Ron,sp are 328 V and 8.8 m??cm2, respectively, for a DG TR metal-oxide-semiconductor field-effect transistor (MOSFET) by simulation. Compared with a conventional SOI LDMOS, a DG TR MOSFET with the same dimensional device parameters as those of the DG TR MOSFET reduces Ron,Sp by 59% and increases BV by 6%. The extended trench gate synchronously acts as an isolation trench between the high-voltage device and low-voltage circuitry in a high-voltage integrated circuit, thereby saving the chip area and simplifying the fabrication processes.