XMSS and Embedded Systems
XMSS and Embedded Systems
复制标题
XMSS 和嵌入式系统
DOI：
10.1007/978-3-030-38471-5_21
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发表时间：
2019
期刊：
影响因子：
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通讯作者：
R. Niederhagen
中科院分区：
文献类型：
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作者：
Wen Wang;Bernhard Jungk;Julian Wälde;Shuwen Deng;Naina Gupta;Jakub Szefer;R. Niederhagen
我们描述了一个基于散列的后量子签名方案XMSS在RISC-V嵌入式处理器上的软硬件协同设计。我们为SHA-256参数集的XMSS参考实现提供软件优化，并提供多个硬件加速器，允许根据个人需求平衡面积使用和性能。通过将我们的硬件加速器集成到RISC-V处理器中，具有最佳时间区域积的版本在3.44秒内生成密钥对（可用于生成\（2^{10}\）签名），与纯软件版本相比，在挂钟时间上实现了超过\（54 \倍\）的加速。对于这样的密钥对，签名生成时间不到10 ms，验证时间不到6 ms，分别带来了超过42倍和17倍的加速。我们在英特尔Cyclone V SoC FPGA上测试和测量了我们实现的周期计数。将我们的XMSS加速器集成到嵌入式RISC-V处理器中表明，可以将基于散列的后量子签名用于各种嵌入式应用。
We describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We provide software optimizations for the XMSS reference implementation for SHA-256 parameter sets and several hardware accelerators that allow to balance area usage and performance based on individual needs. By integrating our hardware accelerators into the RISC-V processor, the version with the best time-area product generates a key pair (that can be used to generate \(2^{10}\) signatures) in 3.44 s, achieving an over \(54 \times \) speedup in wall-clock time compared to the pure software version. For such a key pair, signature generation takes less than 10 ms and verification takes less than 6 ms, bringing speedups of over \(42 \times \) and \(17 \times \) respectively. We tested and measured the cycle count of our implementation on an Intel Cyclone V SoC FPGA. The integration of our XMSS accelerators into an embedded RISC-V processor shows that it is possible to use hash-based post-quantum signatures for a large variety of embedded applications.