Variation Enhancement of Arbiter PUFs with Asymmetric Layout
Variation Enhancement of Arbiter PUFs with Asymmetric Layout
复制标题
具有不对称布局的仲裁器PUF的变异增强
DOI：
10.1109/mwscas.2018.8624035
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发表时间：
2018
期刊：
影响因子：
--
通讯作者：
A. Tyagi
中科院分区：
文献类型：
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作者：
Yunxi Guo;Timothy Dee;A. Tyagi
仲裁器PUF（APUF）是一种流行的物理不可克隆函数（PUF），已被用于许多安全应用。APUF的工艺变化量是影响其分辨率的重要参数。虽然已经从电路设计的角度进行了各种尝试来增加APUF的随机变化，但是几乎没有通过晶体管级布局来增强制造失配的工作。在这项工作中，我们提出了一种新的布局策略，扩大内部芯片的延迟变化的APUF电路的面积中性的方式。该机构将一对赛车延迟单元分开适当的距离。根据Pelgrom的失配模型量化相应的变异增强。Cadence Monte Carlo抽样结果表明，该方案的延迟变化率提高了0。13um技术的128级APUF，最小晶体管尺寸减少了8%，而不会显著影响管芯间汉明距离。
Arbiter PUF (APUF) is a popular style of physical unclonable function (PUF) that has been used in many security applications. The amount of process variation of an APUF is an important parameter strongly influencing its resolution. Although various attempts have been made to increase APUFs’ random variation from the circuit design prospective, little work has been done to enhance manufacturing mismatch through transistor-level layout. In this work, we propose a novel layout strategy for enlarging inner-die delay variation of an APUF circuit in an area neutral manner. The mechanism separates a pair of racing delay units by an appropriate distance. Corresponding variation enhancement is quantified according to Pelgrom’s mismatch model. Cadence Monte Carlo sampling shows the proposed scheme improves delay variation of 0. 13um technology 128-stage APUFs with minimum transistor size by as much as 8% without significantly affecting the inter-die hamming distance.