Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures
Programmable Spike-Timing-Dependent Plasticity Learning Circuits in Neuromorphic VLSI Architectures
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DOI：
10.1145/2658998
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发表时间：
2015-08-01
影响因子：
2.2
通讯作者：
Indiveri, Giacomo
中科院分区：
文献类型：
--
作者：
Azghadi, Mostafa Rahimi;Moradi, Saber;Indiveri, Giacomo
尖峰神经网络的硬件实现为需要紧凑和低功耗计算技术的计算任务提供了有前途的解决方案。由于这些解决方案取决于特定的网络体系结构和使用的学习算法类型，因此开发能够重新配置其网络拓扑和实现不同类型的学习机制的尖峰神经网络设备是很重要的。这里我们提出了一种神经形态的多神经元VLSI器件，它具有片上可编程的基于事件的混合模拟/数字电路；输入/输出信号的基于事件的性质允许使用地址-事件表示基础设施来配置任意网络体系结构，而可编程的突触效能电路允许实现不同类型的基于棘波的学习机制。本文的主要贡献是展示了所提出的可编程神经形态系统如何被配置来实施特定的基于棘波的突触可塑性规则，并描述了如何在认知任务中使用它。具体地说，我们探索了在包括工作站的混合系统中以及当神经形态VLSI设备与其接口时，在线实现不同的尖峰计时可塑性学习规则，并演示了在训练之后，VLSI设备如何作为独立的组件(即，不需要计算机)执行相关模式的二进制分类。
Hardware implementations of spiking neural networks offer promising solutions for computational tasks that require compact and low-power computing technologies. As these solutions depend on both the specific network architecture and the type of learning algorithm used, it is important to develop spiking neural network devices that offer the possibility to reconfigure their network topology and to implement different types of learning mechanisms. Here we present a neuromorphic multi-neuron VLSI device with on-chip programmable event-based hybrid analog/digital circuits; the event-based nature of the input/output signals allows the use of address-event representation infrastructures for configuring arbitrary network architectures, while the programmable synaptic efficacy circuits allow the implementation of different types of spike-based learning mechanisms. The main contributions of this article are to demonstrate how the programmable neuromorphic system proposed can be configured to implement specific spike-based synaptic plasticity rules and to depict how it can be utilised in a cognitive task. Specifically, we explore the implementation of different spike-timing plasticity learning rules online in a hybrid system comprising a workstation and when the neuromorphic VLSI device is interfaced to it, and we demonstrate how, after training, the VLSI device can perform as a standalone component (i.e., without requiring a computer), binary classification of correlated patterns.