An Optimized GIB Routing Architecture with Bent Wires for FPGA
An Optimized GIB Routing Architecture with Bent Wires for FPGA
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DOI：
10.1145/3519599
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发表时间：
2022
影响因子：
2.3
通讯作者：
Lingli Wang
中科院分区：
文献类型：
--
作者：
Kaichuang Shi;Xuegong Zhou;Hao Zhou;Lingli Wang
Field Programmable Gate Arrays (FPGAs) are widely used because of the superiority in flexibility and lower non-recurring engineering cost. How to optimize the routing architecture is a key problem for FPGA architects because it has a large impact on the FPGA area, delay and routability. In academia, the routing architecture is mainly based on the connection blocks (CBs) and switch blocks (SBs), while most researches have focused on the SB architectures, such as Wilton, Universal and Disjoint SB patterns. In this paper, we propose a novel unidirectional routing architecture, general interconnection block (GIB) to improve the FPGA performance. With GIB architecture, logic block (LB) pins can directly connect with the adjacent GIBs without programmable switches. Inside a GIB, LB pins can connect to the routing channel tracks on the four sides of a GIB. In particular, the logic pins from different neighboring LBs that connect to the same GIB can connect with each other with only one programmable switch. Besides, we enhance VTR to support GIB with bent wires and develop a searching framework base on simulated annealing algorithm to search for a near-optimal distribution of wire types. We evaluate the GIB architecture on VTR 8 with the provided benchmark circuits. The experimental results show that the GIB architecture with length-4 wires can achieve 9.5% improvement on the critical path delay and 11.1% improvement on the area-delay product compared to the VTR CB-SB architecture with length-4 wires. After exploring mixed wire types, the optimized GIB architecture can further improve the delay by 16.4% and area-delay product by 17.1% compared to the CB-SB architecture with length-4 wires.
