Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs
Parallel all the time: Plane Level Parallelism Exploration for High Performance SSDs
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DOI：
10.1109/msst.2019.000-5
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发表时间：
2019-05
期刊：
影响因子：
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通讯作者：
Congming Gao;Liang Shi;C. Xue;Cheng Ji;Jun Yang;Youtao Zhang
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文献类型：
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作者：
Congming Gao;Liang Shi;C. Xue;Cheng Ji;Jun Yang;Youtao Zhang
固态驱动器（SSD）是由多层次的并行组织构成的，包括通道、芯片、管芯和平面。在这些并行级别中，作为SSD的最后一级并行的平面级并行具有最严格的限制。只有访问不同平面中相同地址的相同类型的操作才能并行处理。为了最大限度地提高访问性能，已经提出了几个以前的作品，利用平面级并行的主机访问和SSD的内部操作。然而，我们的初步研究表明，平面水平平行度远没有得到很好的利用，应进一步改善。其原因是平面水平平行度的严格限制难以满足。在这项工作中，一个从平面到模具的并行优化框架，提出了开发平面级的并行性，通过巧妙地满足严格的限制。为了实现这一目标，至少有两个挑战。首先，由于主机访问模式总是复杂的，因此同时接收多个相同类型的请求到不同的平面是不常见的。其次，有许多内部活动，如垃圾收集（GC），可能会破坏限制。为了解决上述挑战，在SSD控制器中提出了两种方案：第一，设计了裸片级写入构造方案，以确保每次写入操作总是写入N页数据。其次，在进一步的步骤中，提出了裸片级GC方案以在同一裸片中的所有平面的单元中激活GC。结合管芯级写入和管芯级GC，来自主机写入操作和GC引起的有效页移动的写入访问可以始终并行处理。因此，GC成本和平均写入延迟可以显着降低。实验结果表明，该框架能够显着提高写性能，而不影响读性能。
Solid state drives (SSDs) are constructed with multiple level parallel organization, including channels, chips, dies and planes. Among these parallel levels, plane level parallelism, which is the last level parallelism of SSDs, has the most strict restrictions. Only the same type of operations which access the same address in different planes can be processed in parallel. In order to maximize the access performance, several previous works have been proposed to exploit the plane level parallelism for host accesses and internal operations of SSDs. However, our preliminary studies show that the plane level parallelism is far from well utilized and should be further improved. The reason is that the strict restrictions of plane level parallelism are hard to be satisfied. In this work, a from plane to die parallel optimization framework is proposed to exploit the plane level parallelism through smartly satisfying the strict restrictions all the time. In order to achieve the objective, there are at least two challenges. First, due to that host access patterns are always complex, receiving multiple same-type requests to different planes at the same time is uncommon. Second, there are many internal activities, such as garbage collection (GC), which may destroy the restrictions. In order to solve above challenges, two schemes are proposed in the SSD controller: First, a die level write construction scheme is designed to make sure there are always N pages of data written by each write operation. Second, in a further step, a die level GC scheme is proposed to activate GC in the unit of all planes in the same die. Combing the die level write and die level GC, write accesses from both host write operations and GC induced valid page movements can be processed in parallel at all time. As a result, the GC cost and average write latency can be significantly reduced. Experiment results show that the proposed framework is able to significantly improve the write performance without read performance impact.